The present invention concerns a circuit and a method for calibrating the phase shift between a plurality of digitizers in a data acquisition system.
Many types of data acquisition systems are known, for example transitory recorders and digital oscilloscopes, in which it is necessary to convert one or several analog signals into one or several digital signals capable of being stored in a digital memory and processed by a digital processor. These systems comprise generally an input stage constituted of one or several digitizers and of a memory for digitized data; the processor accesses said memory most often through a bus. In low-frequency systems, this memory can for example be constituted directly by the RAM of a computer. The digitized data are stored in this memory and processed, for example displayed, by the processor of this computer either in real time or later, for example when all the data have been acquired.
More and more often in electronic technology, very high frequency analog signals requiring very fast acquisition systems, for example oscilloscopes, are used. Digitizers are currently made that work with a sampling frequency greater than 500 MHz, for example on the order of 1 GHz or more; it is to be predicted that these current limits will be exceeded with the appearance of better performing components. These digitizers enable by virtue of the Nyquist principle to supply an unambiguous digital representation of analog signals having a maximum frequency of several hundred MHz.
Many applications however require the acquisition of signals with even greater frequencies. The performance and cost of digitizers constitute an obstacle to the making of ultra-fast acquisition systems. Thus the use of systems comprising two digitizers in parallel is known. The sampling times of the digitizers are phase-shifted so that the first digitizer supplies a sequence of samples d0, d2, d4, . . . at the times t0, t2, t4, . . . whereas the other digitizer supplies at the intermediary times t1, t3, t5, . . . a sequence of samples d1, d3, d5, . . . that are phase-shifted by a half-period of sampling p. By combining these two sets of samples, one thus obtains a sequence d0, d1, d2, d3, . . . representing the analog input signal sampled at a rate double that of each digitizer. This principle has also been applied to systems comprising 3, 4 or even more digitizers in order to further increase the speed of the digital sample signal.
The sampling times of the two digitizers must be controlled accurately in order to obtain the required phase shift by p/2. Any deviation of the theoretically required phase leads to errors in the digitized signal, for example to the introduction of harmonics that do not appear in the original signal.
A purpose of the present invention is thus to propose a circuit for analog-to-digital conversion that is improved over the prior art circuits. In particular, a purpose of the present invention is to propose a conversion circuit comprising a plurality of digitizers capable of sampling and digitizing a high-frequency analog input signal, the sampling times of the different digitizers being phase-shifted, the circuit comprising improved means for calibrating the phase shift between a first digitizer and a second digitizer.
Calibration circuits have already been proposed in the prior art. The U.S. Pat. No. 4,736,189 for example describes a method for calibrating sampling phases using a calibration signal whose frequency is derived from the sampling clock by complex operations. Furthermore, this method requires to choose the points on a signal taken as reference that are close to the middle of a slope. This requires either a control of the phase of the calibration signal, or a particular choice of the used digital values.
U.S. Pat. No. 4,763,105 describes another method for calibrating digitizers using complex operations, requiring notably Fourier transforms. Costly digital processing means are thus necessary for implementing this method.
U.S. Pat. No. 4,962,380 describes another method that uses the sampling clock directly for calibrating. This method depends critically on the shape of the calibration signal, which must be for example strictly sinusoidal, which is difficult to ensure. Furthermore, it is necessary to adjust not only the relative phases, but also the absolute phase of the first digitizer.
EP260375 describes a method for calibrating analog-to-digital converters depending on a signal whose frequency must correspond exactly to the sampling frequency. This method is thus very difficult to apply when the sampling frequency is very high.
A purpose of the present invention is thus to propose a calibration method and circuit that are improved over the prior art methods and circuits, in particular a circuit and a method capable of being implemented more easily or more cost-effectively, that do not require complex digital calculation means, and that can also be used for calibrating digitizers with a very high sampling frequency, for example digitizers using a sampling frequency on the order of the GHz.
These purposes are achieved according to the invention by means of an analog-to-digital conversion circuit for high-frequency data acquisition system, comprising a plurality of digitizers capable of sampling and digitizing a high-frequency analog input signal, the sampling times of the different digitizers being phase-shifted, means for calibrating the phase shift between a first digitizer and a second digitizer being provided, wherein said means for calibrating said phase shift determine said phase shift so as to minimize the difference between a sequence of digital values determined by the first digitizer and a sequence of corresponding digital values determined by interpolation of the values supplied by the second digitizer.